Method for Stacking Semiconductor Dies

ABSTRACT

A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer.

TECHNICAL FIELD

The present invention relates generally to a system and method forconnecting semiconductor dies and, more particularly, to a system andmethod for connecting semiconductor dies utilizing a through-siliconvia.

BACKGROUND

Generally, two semiconductor dies may be connected using through-siliconvias (TSVs), which generally require some type of removal of materialfrom the backside of the wafers on which the semiconductor dies areformed. In one method of forming TSVs, a portion of the side of thewafer containing active devices is removed to form one or more holes atleast part of the way through the silicon wafer. After the holes havebeen filled with a conductive material, the backside of the wafer isremoved using a process such as mechanical grinding or etching in orderto expose the conductive material and form a contact through thebackside of the wafer to the front side of the wafer.

However, as materials such as low-k or extremely low-k dielectrics arebeginning to become more widely used, these methods become a problem.These materials are very fragile and do not withstand the stresses fromvarious process steps very well. This problem becomes magnified when thewafers are thinned by mechanical grinding or etching as the dielectricsmay become unable to stand further handling and processing, which mayresult in damage and, eventually, device failure.

As such, what is needed is a new method of forming TSVs that reduce orprevent damage to a thinned wafer during subsequent handling andprocessing.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, andtechnical advantages are generally achieved, by preferred embodiments ofthe present invention which provide for a system and method of stackingdies utilizing through-silicon vias.

In accordance with a preferred embodiment of the present invention, amethod for forming a semiconductor device comprises providing a waferwith a first side, a second side opposite the first side, and at leastone TSV. An edge of the wafer on the second side is protected, and thesecond side of the wafer is thinned to expose the at least one TSVwithout thinning the edge of the second side, thereby forming a thinnedportion and an unthinned edge. The thinned portion of the wafer isseparated from the unthinned edge.

In accordance with another preferred embodiment of the presentinvention, a method for forming a semiconductor device comprisesproviding a wafer comprising a first side and a second side opposite thefirst side, the second side of the wafer comprising a first portion anda second portion surrounding the first portion. At least one TSV isformed in the first portion of the wafer. The second portion of thewafer is protected and the first portion of the wafer is thinned toexpose the at least one TSV without thinning the second portion of thewafer. The thinning forms a thinned first portion of the wafer and anunthinned second portion of the wafer. The thinned first portion of thewafer is separated from the unthinned second portion of the wafer.

In accordance with yet another preferred embodiment of the presentinvention, a method for forming semiconductor devices comprisesproviding a semiconductor wafer having an inner die area surrounded by ascriber line and an outer area immediately adjacent to the scribe line,the semiconductor wafer comprising a first side and a second side.Conductive vias are formed partially through the semiconductor waferfrom the first side, and the inner die area on the second side of thewafer is thinned to expose the conductive vias without thinning theouter area.

An advantage of a preferred embodiment of the present invention is thatthe unthinned portion of the wafer allows the wafer to better handlestresses that are inherent in later processing steps and handling of thewafer. This ability reduces or eliminates potential damage that couldoccur through processing and handling, thereby leading to an increasedyield of dies.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawing, in which:

FIG. 1 illustrates a wafer with through-silicon vias formed partiallythrough the wafer in accordance with an embodiment of the presentinvention;

FIGS. 2A-2B illustrate cross-sectional and plan views, respectively, ofa thinning of a portion of the wafer in accordance with an embodiment ofthe present invention;

FIGS. 3A-3B illustrate cross-sectional and plan views, respectively, ofthe bonding of a second die to the wafer in accordance with anembodiment of the present invention;

FIG. 4 illustrates the placement of a fill material over the second diein accordance with an embodiment of the present invention; and

FIG. 5 illustrates the separation of the bonded first die and second diefrom the edge of the wafer in accordance with an embodiment of thepresent invention.

Corresponding numerals and symbols in the different figures generallyrefer to corresponding parts unless otherwise indicated. The figures aredrawn to clearly illustrate the relevant aspects of the preferredembodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

The present invention will be described with respect to preferredembodiments in a specific context, namely stacked dies utilizingthrough-silicon vias in a semiconductor wafer. The invention may also beapplied, however, to other thin wafer handling processes.

With reference now to FIG. 1, there is shown a cross-sectional view of awafer 100 with a front side 115 and a backside 1 17. The wafer 100preferably has a plurality of first semiconductor dies 102 (outlined bythe dashed lines) formed in a die area 119 of the wafer 100, a scribeline 120 adjacent to the die area 119 of the wafer 100, and an edge 121preferably immediately adjacent the scribe line 120 of the wafer 100.However, for the sake of clarity in the presentation of the presentinvention, FIGS. 1, 2A, 3A, and 4-5 clearly show only a single firstsemiconductor die 102, and it is to be understood that, while only asingle first semiconductor die 102 is shown, any number of firstsemiconductor dies 102 may be formed on the wafer 100 while remainingwithin the scope of the present invention.

The first semiconductor die 102 preferably comprises a substrate 101,active devices 104, metallization layers 103, contact pads 105,underbump metallization (UBM) 107, contact bumps 108, andthrough-silicon vias (TSVs) 109. The substrate 101 may comprise bulksilicon, doped or undoped, or an active layer of a silicon-on-insulator(SOI) substrate. Generally, an SOI substrate comprises a layer of asemiconductor material such as silicon, germanium, silicon germanium,SOI, silicon germanium on insulator (SGOI), or combinations thereof.Other substrates that may be used include multi-layered substrates,gradient substrates, or hybrid orientation substrates.

The active devices 104 are represented on FIG. 1 as a single transistor.However, as one of skill in the art will recognize, a wide variety ofactive devices such as capacitors, resistors, inductors and the like maybe used to generate the desired structural and functional requirementsof the design. The active devices 104 may be formed using any suitablemethods either within or else on the surface of the substrate 101.

The TSVs 109 are preferably formed by applying and developing a suitablephotoresist (not shown), and then etching the substrate 201 to generateTSV openings (filled later as discussed below). Preferably, the openingsfor the TSVs 109 at this stage are formed so as to extend into thesubstrate 101 at least further than the active devices 104 formed withinand on the substrate 101, and preferably to a depth at least greaterthan the eventual desired height of the finished first semiconductor die102. Accordingly, while the depth is dependent upon the overall designof the first semiconductor die 102, the depth is preferably betweenabout 1 μm and about 700 μm below the surface on the substrate 101, witha preferred depth of about 50 μm. The openings for the TSVs 109 arepreferably formed to have a diameter of between about 1 μm and about 100μm, with a preferred diameter of about 6 μm.

Once the openings for the TSVs 109 have been formed, the openings forthe TSVs 109 are preferably filled with a barrier layer 11 1 and aconductive material 1 13. The barrier layer 111 preferably comprises aconductive material such as titanium nitride, although other materials,such as tantalum nitride, titanium, a dielectric, or the like mayalternatively be utilized. The barrier layer 111 is preferably formedusing a CVD process, such as PECVD. However, other alternativeprocesses, such as sputtering or metal organic chemical vapor deposition(MOCVD), may alternatively be used. The barrier layer 111 is preferablyformed so as to contour to the underlying shape of the opening for theTSVs 109.

The conductive material 113 preferably comprises copper, although othersuitable materials such as aluminum, alloys, doped polysilicon,combinations thereof, and the like, may alternatively be utilized. Theconductive material 113 is preferably formed by depositing a seed layerand then electroplating copper onto the seed layer, filling andoverfilling the openings for the TSVs 109. Once the openings for theTSVs 109 have been filled, excess barrier layer 111 and excessconductive material 113 outside of the openings for the TSVs 109 arepreferably removed through a grinding process such as chemicalmechanical polishing (CMP), although any suitable removal process may beused.

The metallization layers 103 are preferably formed over the substrate101 and the active devices 104 and are designed to connect the variousactive devices 104 to form functional circuitry. The metallizationlayers 103 are preferably formed of alternating layers of dielectric andconductive material and may be formed through any suitable process (suchas deposition, damascene, dual damascene, etc.). Preferably, there areat least four layers of metallization separated from the substrate 101by at least one interlayer dielectric layer (ILD), but the precisenumber of metallization layers 103 is dependent upon the design of thefirst semiconductor die 102.

The contact pads 105 are preferably formed to connect the metallizationlayers 103 to exterior input/output connections, such as the UBM 107.The contact pads 105 are preferably formed of aluminum, although othermaterials, such as aluminum alloy, aluminum copper, copper, combinationsof these, and the like, may alternatively be used. Further, the contactpads 105 may be formed in a variety of methods depending upon thematerial used. For example, if aluminum is used the contact pads 105 arepreferably formed by forming a layer of aluminum over the metallizationlayers 103, and then using a suitable technique such as photolithographyand chemical etching to pattern the aluminum into the contact pads 105.Alternatively, if copper is used the contact pads 105 are preferablyformed by initially forming a dielectric layer 106, forming openingsinto the dielectric layer 106, depositing a barrier layer and a seedlayer (not shown), overfilling the openings with copper, and then usinga grinding process such as CMP to remove excess copper outside of theopenings to form the contact pads 105. Any suitable process for formingthe contact pads 105 may be used and all of these processes are fullyintended to be included within the scope of the present invention.

The UBMs 107 are intended to act as an intermediary between the contactpads 105 and the contact bumps 108. The UBMs 107 are preferably formedso as to make physical and electrical contact with the contact pads 105.The UBMs 107 are preferably made of at least three layers of conductivematerials, such as a layer of chrome, a layer of a chrome-copper alloy,and a layer of copper, with an optional layer of gold over the top ofthe copper layer. However, one of skill in the art will recognize thatthere are many suitable arrangements of materials and layers, such as anarrangement of titanium/titanium tungsten/copper or an arrangement ofcopper/nickel/gold, that are suitable for the formation of the UBMs 107.Any suitable materials or layers of material that may be used for theUBMs 107 are fully intended to be included within the scope of thecurrent application.

The UBMs 107 are preferably created by forming each layer conformallyover the contact pads. The forming of each layer is preferably performedusing a CVD process, such as PECVD, although other processes offormation, such as sputtering, evaporation, or plating process, mayalternatively be used depending upon the desired materials. Each of thelayers within the UBMs 107 preferably has a thickness of between about10 μm and about 100 μm, with a preferred thickness of about 45 μm. Oncethe desired layers have been formed, portions of the layers are thenremoved through a suitable photolithographic masking and etching processto remove the undesired material and to leave the patterned UBMs 107.

The contact bumps 108 preferably comprise a material such as tin, orother suitable materials, such as silver or copper. In an embodiment inwhich the contact bumps 108 are tin solder bumps, the contact bumps 108may be formed by initially forming a layer of tin through any suitablemethod such as evaporation, electroplating, printing, solder transfer,ball placement, etc, to a preferred thickness of about 100 μm. Once alayer of tin has been formed on the structure, a reflow is preferablyperformed in order to shape the material into the desired bump shape.

The scribe line 120 of the wafer preferably surrounds the plurality ofsemiconductor dies 102. The scribe line 120 is preferably formed by notplacing functional structures (such as active devices 104) into the areaintended for the scribe line 120. Other structures, such as test pads ordummy metals used for planarization, could be placed into the scribeline 120, but would not be necessary for the functioning of thesemiconductor dies 102 once the semiconductor dies 102 have been cutfrom the wafer 100. The scribe lines 120 preferably have a width ofbetween about 20 μm and about 180 μm, with a preferred width of about 80μm.

However, as one of skill in the art will recognize, the abovedescription, while exemplary, is also merely illustrative, and shouldnot be viewed as limiting the present invention to just this embodiment.Numerous variations in the initial structure of the first semiconductordie 102 may alternatively be used. For example, a structure wherein theTSVs 109 extend not only through the substrate 101 but are also formedto extend through one or more of the metallization layers 103 may alsobe utilized. Any of these embodiments, and any other suitableembodiments, are fully intended to be within the scope of the scope ofthe present invention.

FIG. 2A illustrates a thinning of the backside 117 of the wafer 100. Inthis embodiment the wafer 100 is preferably placed into a bottom portion203 of a chuck 201 with the front side 115 downward. A top portion 205of the chuck 201 is then preferably connected to the bottom portion 203of the chuck 201, with the top portion 205 of the chuck 201 overlyingand protecting the edge 121 of the wafer 100 immediately adjacent to thescribe line 120 while leaving the scribe line 120 and the die area 119exposed. A series of one or more seals (not shown) is also preferablyused to ensure an adequate seal between the chuck 201 and the wafer 100,and to ensure that no contaminants can reach the edge 121 or thebackside 117 of the wafer 100.

However, as one of ordinary skill in the art will recognize, this chuck201 is only illustrative of a single suitable method for protecting thefront side 115 of the wafer 100 and those portions of the backside 117of the wafer 100 that are preferably not removed. Any other suitablemethod, such as forming one or more photoresists layers or usingadhesive tape to protect the areas, may alternatively be utilized. Allof these methods are fully intended to be included within the scope ofthe present invention.

Once the edge 201 of the backside 117 of the wafer 100 has beenprotected, the unprotected die area 119 of the wafer 100 is preferablythinned so as to expose the TSVs 109 and to transfer the pattern of thechuck 201 onto the edge 121 of the wafer 100. The thinning is preferablyperformed using a two step wet etch process: a bulk removal etch and afinishing etch. The bulk removal etch is preferably performed using amixture of nitric acid (HNO₃), sulfuric acid (H₂SO₄), hydrogen fluoride(HF), and phosphoric acid (H₃PO₄) commercially known as Spin-Etch D inorder to remove the bulk of the wafer 100 down to the TSVs 109.Preferably, given a 700 μm wafer thickness, the thinning preferablyremoves between about 600 μm and about 670 μm, with a preferred removalof about 650 μm.

Once the bulk removal has been performed, an overetch of the wafer 100is preferably performed such that a portion of the barrier layer 111 isremoved and the TSVs 109 extend away from the remaining wafer 100. Theoveretch is preferably performed using an etchant, such astetramethylammonium nhydroxide (TMAH) which has a very high selectivitybetween the material of the wafer (e.g., silicon) and the conductivematerial 113 of the TSV 109 (e.g., copper). The overetch preferablyremoves the material of the wafer such that the TSVs 109 extend betweenabout 10 μm and about 0.5 μm from the wafer 100, with a preferredextension of about 1 μm.

FIG. 2B illustrates a plan view of the backside 117 of the wafer 100after the backside 117 has been thinned and the chuck 201 has beenremoved. As illustrated, the chuck 201 preferably forms an edge 121 thatexpands as far as feasible from the outer edge without interfering withthe outermost scribe line 120 or the plurality of semiconductor dies 102(represented by the dashed lines) in the die area 119. Accordingly, theinner boundary of the edge 121 preferably conforms to the shape of thedie area 119.

FIG. 3A illustrates the bonding of a second semiconductor die 300 to thefirst semiconductor die 102. The second semiconductor die 300 preferablycontains structures similar to the wafer 100, such as a second substrate301, a second set of active devices 303, a second set of metallizationlayers 305, and second contact bumps 307 on a first side of the secondsemiconductor die 300, and these structures are preferably made in asimilar fashion as described above with respect to FIG. 1. However, thesecond semiconductor die 300 is not intended to be limited to just thisembodiment, and any suitable device that is desired to be connected tothe first semiconductor die 102 may alternatively be used.

Preferably, the second semiconductor die 300 is placed within a cavityformed from the edge 121 and the thinned backside 117 of the wafer 100.Additionally, the first semiconductor die 102 and wafer 100 arepreferably aligned such that the second contact pads 307 are inalignment with the TSVs 109. Once aligned, the second contact bumps 307and the TSVs 109 are then preferably bonded together by contacting thesecond contact bumps 307 to the TSVs 109 and performing a reflow toreflow the material of the second contact bumps 307 and bond to the TSVs109. Any suitable method of bonding, however, such as copper-copperbonding, may alternatively be utilized to bond the second semiconductordie 300 to the first semiconductor die 102.

An underfill material 309 is preferably injected or otherwise formed inthe space between the first semiconductor die 102 and the secondsemiconductor die 300. The underfill material 309 may, for example,comprise a liquid epoxy that is dispensed between the firstsemiconductor die 102 and the second semiconductor die 300, and thencured to harden. This underfill material 309 is used to prevent cracksfrom being formed in the contact bumps 307, wherein cracks are typicallycaused by thermal stresses.

Alternatively, either a deformable gel or silicon rubber could be formedbetween the first semiconductor die 102 and the second semiconductor die300 in order to help prevent cracks from occurring within the contactbumps 307. This gel or silicon rubber may be formed by injecting orotherwise placing the gel or rubber between the first semiconductor die102 and the second semiconductor die 300. The deformable gel or siliconrubber can provide greater stress relief during subsequent processing.

FIG. 3B illustrates a plan view of the backside 117 of the wafer 100after the second semiconductor die 300 has been attached. As isapparent, multiple second semiconductor dies 300 are preferably attachedto individual ones of the plurality of first semiconductor dies 102formed on the wafer 100 (not visible in FIG. 3A but located under thesecond semiconductor dies 300). As is also apparent, the edge 121 of thewafer 100 preferably extends from the outer edge of the wafer 100 as faras feasible towards the die area 119, thereby preferably conforming tothe shape of the die area 119.

FIG. 4 illustrates an optional addition of a filler material 401 tofurther protect the bonded first semiconductor die 102 and secondsemiconductor die 300. The filler material is preferably placed to fillin the area between the edge 121 and the second semiconductor die 300and also preferably covers the second semiconductor die 300. The fillermaterial 401 preferably comprises a molding compound, but mayalternatively be an epoxy, polyimide, or the like, and is preferablyinjected or otherwise placed prior to being hardened using a thermalcure process. Any other material and processes, however, that may beused to protect the first semiconductor die 102 and the secondsemiconductor die 300 may alternatively be used.

FIG. 5 illustrates that, once the second semiconductor dies 300 havebeen bonded to the first semiconductor dies 102 and the optional fillermaterial 401 has been placed (or not), the individually bonded firstsemiconductor dies 102 are then preferably singulated from the wafer100. The singulation is preferably performed by using a saw blade (notshown) to slice the wafer 100 along the areas between the individualfirst semiconductor dies 102, thereby separating each individual firstsemiconductor die 102 from the wafer 100. This singulation processadditionally separates each of the individual first semiconductor die102 from the edge 121 of the wafer 100, thereby leaving the singulatedfirst semiconductor dies 102 without the edge 121 of the wafer 100.

By leaving the edge 121 thicker than the remaining portion of thethinned wafer 100, the wafer 100 may better withstand the stresses fromfurther processing, handling, and transport. Further, by extending theedge 121 all the way to the die area 119, more of the wafer 100 remainsthicker, thereby improving the ability of the wafer to withstand stresseven further. Accordingly, fewer of the first semiconductor dies 102formed on the wafer 100 will be damaged, leading to an increase inoverall yield.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made herein without departing from the spirit andscope of the invention as defined by the appended claims. For example,different methods of protecting the edge from being removed are fullyintended to be included within the scope of the present invention. Asanother example, the materials used for the underfill and fill materialsmay vary greatly while still remaining within the scope of the presentinvention.

Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

1. A method for forming a semiconductor device, the method comprising: providing a wafer with a first side, a second side opposite the first side, the wafer comprising at least one conductive plug passing through at least a portion of the wafer; protecting an edge of the wafer on the second side; thinning the second side of the wafer to expose the at least one conductive plug without thinning the edge of the second side, thereby forming a thinned portion and an unthinned edge; and separating the thinned portion of the wafer from the unthinned edge.
 2. The method of claim 1, wherein the edge follows the contours of a die area of the wafer.
 3. The method of claim 1, further comprising bonding a semiconductor die to the thinned portion of the wafer.
 4. The method of claim 3, further comprising placing an underfill material between the semiconductor die and the thinned portion of the wafer.
 5. The method of claim 3, wherein the bonding the semiconductor die to the thinned portion comprises placing the semiconductor die into a cavity formed by the edge of the wafer and the thinned portion of the wafer.
 6. The method of claim 5, further comprising encapsulating the semiconductor die with a fill material.
 7. The method of claim 1, wherein the protecting the edge of the wafer comprises placing the wafer into a chuck.
 8. A method for forming a semiconductor device, the method comprising: providing a wafer comprising a first side and a second side opposite the first side, the second side of the wafer comprising a first portion and a second portion surrounding the first portion; forming at least one conductive plug in the first portion of the wafer; protecting the second portion of the wafer; thinning the first portion of the wafer to expose the at least one conductive plug without thinning the second portion of the wafer, the thinning forming a thinned first portion of the wafer and an unthinned second portion of the wafer; and separating the thinned first portion of the wafer from the unthinned second portion of the wafer.
 9. The method of claim 8, further comprising bonding a semiconductor die to the thinned first portion of the wafer.
 10. The method of claim 9, further comprising placing an underfill material between the semiconductor die and the thinned first portion of the wafer.
 11. The method of claim 9, wherein the bonding a semiconductor die to the thinned portion of the wafer comprises placing the semiconductor die into a cavity formed by the unthinned portion of the wafer and the thinned portion of the wafer.
 12. The method of claim 9, further comprising placing a filler material between the semiconductor die and the unthinned portion of the wafer.
 13. The method of claim 8, wherein the thinning the first portion of the wafer comprises a wet etch.
 14. The method of claim 8, wherein the unthinned portion of the wafer conforms to an area of the wafer that contains a plurality of semiconductor dies.
 15. A method for forming semiconductor devices: providing a semiconductor wafer having an inner die area surrounded by a scribe line and an outer area immediately adjacent to the scribe line, the semiconductor wafer comprising a first side and a second side; forming conductive vias partially through the semiconductor wafer from the first side; and thinning the inner die area on the second side of the wafer to expose the conductive vias without thinning the outer area.
 16. The method of claim 15, further comprising bonding a semiconductor die to the inner die area of the wafer.
 17. The method of claim 16, further comprising placing an underfill material between the semiconductor die and the inner die area of the wafer.
 18. The method of claim 16, wherein the semiconductor die is placed within a cavity formed by the inner die area and the outer area.
 19. The method of claim 16, further comprising covering the semiconductor die with a fill material.
 20. The method of claim 16, further comprising separating the inner die area from the unthinned outer area. 